2012 (Phase 1), 2013 (Phase 2) - Split Foundry Asynchronous FPGA
Test chip, the details about this chip will be disclosed in future publications.
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Out-of-house tools:
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Micromagic MAX layout editor
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Mentor Graphics Calibre DRC/nmLVS/PEX
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Synopsys HSIM
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A Split-Foundry Asynchronous FPGA
October 2012: Baseband Global Positioning System (GPS) core
Implementation of the GPS described in the 2011 publication: A low Power Asynchronous GPS Baseband Processor.
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Digital simulation:
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ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator
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ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator
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Analog simulation:
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Synopsys VCS-HSIM
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Synthesis:
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ACT-Act2v: ACT to Verilog compiler
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Synopsys Design Compiler
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Layout:
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Undisclosed tool created at Cornell --- to be disclosed soon
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Micromagic MAX layout editor
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Calibre nmLVS - DRC - PeX
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Angel Adviser: Review processes, check design, floorplanning aid, sanity checks of the design
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Co-creator of confidential tool and full support for the GPS
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Tool support
2011: Ultra-Low Power embedded Processor
This chip embodies a fully-implemented ultra-low power event-driven microcontroller targeted at the bursty workloads of the sensor network application space. We employ an event-driven design methodology at both the microarchitectural and circuit levels to provide 93 MIPS at 1.2V and 47 MIPS at 0.95V, consuming 47pJ and 29pJ per operation respectively. Idle power is only 10 μW. Compared to state-of-the-art processors in its class, our 90nm test chip is on the Pareto-optimal front of the energy- performance space.
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Technology node: confidential
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Architectural Simulator
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CAST-CHPSim: Caltech Asynchronous Synthesis Tools - Communicating Hardware Processes Simulator
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Digital simulation:
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ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator
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ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator
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HACKT : Hierarchical Asynchronous Circuit Kompiler Toolkit - Production rule simulator - fast prototyping
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Analog simulation:
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Synopsys VCS-HSIM
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Layout:
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Micromagic MAX layout editor (4/5 chip)
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Cornell PandR: Cornell Place and Route Tools (discontinued tool)
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Cadence Virtuoso layout editor (1/5 chip)
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Cadence Virtuoso schematic editor
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Calibre nmLVS - DRC - PeX
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Static Power Reduction techniques for Asynchronous Circuits
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ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes
2010 - Neurosynaptic core
For the full description, please see the Cornell website on link:http://vlsi.cornell.edu/bio.php [Biologically-Inspired Cognitive Processing]. There are multiple publications associated with this project sponsored by DARPA and led by IBM Corp.
Digital implementation of a flexible brain-like architecture. This project is intended to leverage the density of VLSI to enable circuit-level simulation of a neurosynaptic fabric.
This project was done in collaboration with IBM Research Almaden and on the Cornell end it was led by Filipp Akopyan and Nabil Imam and was supported by the core team of myself, Jonathan Tse, Benjamin Hill and Robert Karmazin.
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Technology node: SOI 45nm
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Tool support
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Technology file creation
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Layout
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Extracted simulation of demuxer
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Digital simulation:
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ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator
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ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator
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Analog simulation:
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Synopsys VCS-HSIM
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Layout:
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Micromagic MAX layout editor (used at Cornell only)
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Cadence Virtuoso layout editor (mainly used at IBM)
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Cornell PandR: Cornell Place and Route Tools
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Calibre nmLVS - DRC - PeX
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2010 - Asynchronous FPGA
A Reconfigurable fabric (FPGA) integrated with a General Purpose Logic
The 2010 revision was led by Benjamin Hill and included several revisions to the original FPGA project at Cornell University. The details of these revisions will be delivered in upcoming publications.
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Layout of part of the datapaths.
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Extracted simulation part of the datpaths.
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Tool support
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Digital simulation:
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ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator
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ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator
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Analog simulation:
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Synopsys VCS-HSIM
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Layout:
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Micromagic MAX layout editor
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Cornell PandR: Cornell Place and Route Tools (tool discontinued)
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Calibre nmLVS - DRC - PeX
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2007 - Resilient Asynchronous Circuits
Test chip to demonstrate the stability of asynchronous circuits at different temperatures
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Technology node: CMOS SiGe 0.5um .My Tasks
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Pre-layout verification
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Layout
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Pad frame
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Post-layout verification
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Testing
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Digital simulation:
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CAST-Prsim: Caltech Asynchronous Synthesis Tools - Production Rule simulator
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Analog simulation:
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Cadence Spectre spice simulator
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Layout
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Magic VLSI layout editor
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Cadence Virtuoso layout editor
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2006 - 3D characterization
The Asynchronous group designed this chip designed to characterize the performance degradation due to increased heat resistance between the dies and the heat sink.
This chip illustrates the process variations of 3-D integration.
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Technology node: MIT-LL 3-Dv2 TSV SOI 180nm
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1.5um tungsten-filled TSV
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3 stacked dies
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TSV backplane connection
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Designer of Analog temperature sensors
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Top-level layout
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Post-layout verification
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Testing
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Data Analysis
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Cryogenic tests
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Oven tests
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CAST-Prsim: Caltech Asynchronous Synthesis Tools
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Magic VLSI layout editor
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Cadence Virtuoso layout editor
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Synopsys Nanosim Fast-Spice simulator