2012 (Phase 1), 2013 (Phase 2) - Split Foundry Asynchronous FPGA

Description

Test chip, the details about this chip will be disclosed in future publications.

images/fpga_tic.jpg

Tools
  • Out-of-house tools:

    • Micromagic MAX layout editor

    • Mentor Graphics Calibre DRC/nmLVS/PEX

    • Synopsys HSIM

Related Publications
  • A Split-Foundry Asynchronous FPGA

October 2012: Baseband Global Positioning System (GPS) core

Description

Implementation of the GPS described in the 2011 publication: A low Power Asynchronous GPS Baseband Processor.

Tools
  • Digital simulation:

    • ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator

    • ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator

  • Analog simulation:

    • Synopsys VCS-HSIM

  • Synthesis:

    • ACT-Act2v: ACT to Verilog compiler

    • Synopsys Design Compiler

  • Layout:

    • Undisclosed tool created at Cornell --- to be disclosed soon

    • Micromagic MAX layout editor

    • Calibre nmLVS - DRC - PeX

My Task
  • Angel Adviser: Review processes, check design, floorplanning aid, sanity checks of the design

  • Co-creator of confidential tool and full support for the GPS

  • Tool support

2011: Ultra-Low Power embedded Processor

Description

This chip embodies a fully-implemented ultra-low power event-driven microcontroller targeted at the bursty workloads of the sensor network application space. We employ an event-driven design methodology at both the microarchitectural and circuit levels to provide 93 MIPS at 1.2V and 47 MIPS at 0.95V, consuming 47pJ and 29pJ per operation respectively. Idle power is only 10 μW. Compared to state-of-the-art processors in its class, our 90nm test chip is on the Pareto-optimal front of the energy- performance space.

images/snap_with_mem_m1-4_labels.jpg

  • Technology node: confidential

Tools
  • Architectural Simulator

    • CAST-CHPSim: Caltech Asynchronous Synthesis Tools - Communicating Hardware Processes Simulator

  • Digital simulation:

    • ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator

    • ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator

    • HACKT : Hierarchical Asynchronous Circuit Kompiler Toolkit - Production rule simulator - fast prototyping

  • Analog simulation:

    • Synopsys VCS-HSIM

  • Layout:

    • Micromagic MAX layout editor (4/5 chip)

    • Cornell PandR: Cornell Place and Route Tools (discontinued tool)

    • Cadence Virtuoso layout editor (1/5 chip)

    • Cadence Virtuoso schematic editor

    • Calibre nmLVS - DRC - PeX

Related Publications
  • Static Power Reduction techniques for Asynchronous Circuits

  • ULSNAP: An Ultra-low Power Event-Driven Microcontroller for Sensor Network Nodes

2010 - Neurosynaptic core

Description

For the full description, please see the Cornell website on link:http://vlsi.cornell.edu/bio.php [Biologically-Inspired Cognitive Processing]. There are multiple publications associated with this project sponsored by DARPA and led by IBM Corp.

Digital implementation of a flexible brain-like architecture. This project is intended to leverage the density of VLSI to enable circuit-level simulation of a neurosynaptic fabric.

This project was done in collaboration with IBM Research Almaden and on the Cornell end it was led by Filipp Akopyan and Nabil Imam and was supported by the core team of myself, Jonathan Tse, Benjamin Hill and Robert Karmazin.

Synapse chip

images/scheduler_m1-4_labels.jpg

  • Technology node: SOI 45nm

My tasks
  • Tool support

  • Technology file creation

  • Layout

  • Extracted simulation of demuxer

Tools
  • Digital simulation:

    • ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator

    • ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator

  • Analog simulation:

    • Synopsys VCS-HSIM

  • Layout:

    • Micromagic MAX layout editor (used at Cornell only)

    • Cadence Virtuoso layout editor (mainly used at IBM)

    • Cornell PandR: Cornell Place and Route Tools

    • Calibre nmLVS - DRC - PeX

2010 - Asynchronous FPGA

Description

A Reconfigurable fabric (FPGA) integrated with a General Purpose Logic

The 2010 revision was led by Benjamin Hill and included several revisions to the original FPGA project at Cornell University. The details of these revisions will be delivered in upcoming publications.

images/fpga.jpg

My tasks
  • Layout of part of the datapaths.

  • Extracted simulation part of the datpaths.

  • Tool support

Tools
  • Digital simulation:

    • ACT-Prsim: Asynchronous Circuit Toolkit - Production Rule simulator

    • ACT-Netgen: Asynchronous Circuit Toolkit - Netlist Generator

  • Analog simulation:

    • Synopsys VCS-HSIM

  • Layout:

    • Micromagic MAX layout editor

    • Cornell PandR: Cornell Place and Route Tools (tool discontinued)

    • Calibre nmLVS - DRC - PeX

2007 - Resilient Asynchronous Circuits

images/2007_chip.jpg

Description

Test chip to demonstrate the stability of asynchronous circuits at different temperatures

  • Technology node: CMOS SiGe 0.5um .My Tasks

  • Pre-layout verification

  • Layout

  • Pad frame

  • Post-layout verification

  • Testing

Tools
  • Digital simulation:

    • CAST-Prsim: Caltech Asynchronous Synthesis Tools - Production Rule simulator

  • Analog simulation:

    • Cadence Spectre spice simulator

  • Layout

    • Magic VLSI layout editor

    • Cadence Virtuoso layout editor

2006 - 3D characterization

3D TSV test chip
Description

The Asynchronous group designed this chip designed to characterize the performance degradation due to increased heat resistance between the dies and the heat sink.

This chip illustrates the process variations of 3-D integration.

  • Technology node: MIT-LL 3-Dv2 TSV SOI 180nm

    • 1.5um tungsten-filled TSV

    • 3 stacked dies

    • TSV backplane connection

My Tasks
  • Designer of Analog temperature sensors

  • Top-level layout

  • Post-layout verification

  • Testing

  • Data Analysis

  • Cryogenic tests

  • Oven tests

Tools
  • CAST-Prsim: Caltech Asynchronous Synthesis Tools

  • Magic VLSI layout editor

  • Cadence Virtuoso layout editor

  • Synopsys Nanosim Fast-Spice simulator